Conventionally, in some semiconductor modules in which submounts are packaged, electrodes are formed not only on an element mounting surface of the submount but also on a side surface portion of the submount.
Examples of conventional techniques include a module like one shown in FIG. 26. This module 109 includes a main substrate 110, an IC 111 on the main substrate 110, and a submount 100 on the main substrate 110. The submount 100 includes a semiconductor element 104 on an element mounting surface.
In the module shown in FIG. 26, a through-hole electrode and an element mounting electrode are formed as an electrode 102 in the submount 100. An electrical connection between the IC 111 and the semiconductor element 104 is achieved by connecting the IC 111 and the electrode 102 by an AU wire 112.
However, in the module shown in FIG. 26, the electrode 102 is formed over two surfaces of a substrate 101 and an electrode area is large. Accordingly, a parasitic capacitance is large. Furthermore, the module shown in FIG. 26 also includes a through-hole land portion and inevitably has a large pitch, so that there is a problem that a high-density submount cannot be manufactured.